// DCFIFO_10bit_64.v

// Generated using ACDS version 19.1 670

`timescale 1 ps / 1 ps
module DCFIFO_10bit_64 (
		input  wire [9:0] data,  //  fifo_input.datain
		input  wire       wrreq, //            .wrreq
		input  wire       rdreq, //            .rdreq
		input  wire       wrclk, //            .wrclk
		input  wire       rdclk, //            .rdclk
		input  wire       aclr,  //            .aclr
		output wire [9:0] q      // fifo_output.dataout
	);

	DCFIFO_10bit_64_fifo_191_nq37gli fifo_0 (
		.data  (data),  //  fifo_input.datain
		.wrreq (wrreq), //            .wrreq
		.rdreq (rdreq), //            .rdreq
		.wrclk (wrclk), //            .wrclk
		.rdclk (rdclk), //            .rdclk
		.aclr  (aclr),  //            .aclr
		.q     (q)      // fifo_output.dataout
	);

endmodule
